Invention Grant
US07750712B2 Timing control circuit, timing generation system, timing control method and semiconductor memory device
有权
定时控制电路，定时生成系统，定时控制方法和半导体存储器件
- Patent Title: Timing control circuit, timing generation system, timing control method and semiconductor memory device
- Patent Title (中): 定时控制电路，定时生成系统，定时控制方法和半导体存储器件
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Application No.: US12314207Application Date: 2008-12-05
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Publication No.: US07750712B2Publication Date: 2010-07-06
- Inventor: Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
- Applicant: Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2007-317161 20071207
- Main IPC: H03H11/26
- IPC: H03H11/26
Abstract:
A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
Public/Granted literature
- US20090146716A1 Timing control circuit, timing generation system, timing control method and semiconductor memory device Public/Granted day:2009-06-11
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