Invention Grant
US07750830B2 Calibration device and method thereof for pipelined analog-to-digital converter 有权
用于流水线模数转换器的校准装置及其方法

Calibration device and method thereof for pipelined analog-to-digital converter
Abstract:
A calibration device includes a comparison unit, a counting unit, a memory, and a compensation circuit. A residue of a sub analog-to-digital converter is compared with a first and a second voltage by the comparison unit for generating a comparison result. A number of times of the residue voltage, out of bounds defined by the first and the second voltage, is counted by the counting unit in an ith period according to the comparison result. The number of times of the residue voltage out of the bounds in an (i−1)th period is stored in the memory. A clock of the sub ADC is adjusted by the compensation circuit into a direction based on the number of times of the residue voltage out of the bounds in the ith period and the number of times of the residue voltage out of the bounds in the (i−1)th period.
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