In a pipelined analog-to-digital (AD) converter, if logically incongruent signals S1 and S2 are output from an AD converter section of a converter stage of the AD converter, a digital-to-analog converter (DAC) section is to be prevented from erroneously operating. When a logically incongruent combination of signals S1 and S2, such as S1=“H” and S2=“L”, is output from comparators that compare an input voltage VI to reference voltages +REF/4 and −REF/4, an encoder outputs a signal corresponding to a normal signal combination (S1=“L” and S2=“H”) to generate signals X, Y and Z that control switches of the DAC section. This eliminates the risk that the switches shall be turned on simultaneously, thus preventing the erroneous operation of the DAC section.