Invention Grant
US07751256B2 Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory 有权
防止非易失性存储器的高压锁存器的高压电源劣化的方法和装置

Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory
Abstract:
An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg of the latch and ground to limit leakage current. A large number of latches are connected in parallel and their accumulated leakage currents are limited by the switching circuit to prevent overload of a high-voltage generator, such as a charge pump circuit, for the high-voltage latch, so that data can be properly written in the memory cells of the non-volatile memory.
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