In a semiconductor device including a plurality of memory units and a method of testing the same, the semiconductor device includes a plurality of memory units each comprising a plurality of input lines; and an input unit configured to provide a plurality of test signals to the input lines, respectively, included in each of the memory units in response to a test enable signal. A data input/output unit can be configured to receive Z-bit data from test equipment and to distribute the Z-bit data to the plurality of memory units in response to the test enable signal, where Z is a natural number. The data input/output unit outputs K-bit data, which are output from each of the plurality of memory units, through data input/output lines included in the plurality of memory units in response to the test enable signal, where K≦Z and K is a natural number.