A layout structure of a Sub-Word Line Driver (SWD) and a forming method thereof. A layout structure of an SWD may include first through fourth metal-oxide-semiconductor (MOS) transistors. The layout structure may include a first area including an active area of the first MOS transistor, wherein a gate-poly (GP) of the first MOS transistor may be disposed in a predefined direction over a portion of the first area. The layout structure may also include a second area including an active area of the second through fourth MOS transistors. Each GP of the second through fourth MOS transistors may be disposed in parallel to each other. The GP of the first MOS transistor disposed in the predefined direction may be substantially perpendicular to each GP of the second through fourth MOS transistors. The layout structure of an SWD can improve a driving capability without increasing an area of the chip.