Invention Grant
- Patent Title: Fault tolerant duplex computer system and its control method
- Patent Title (中): 容错双工计算机系统及其控制方法
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Application No.: US11312116Application Date: 2005-12-20
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Publication No.: US07751310B2Publication Date: 2010-07-06
- Inventor: Masahiro Yoshida
- Applicant: Masahiro Yoshida
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Priority: JP2004-367748 20041220
- Main IPC: G01R31/08
- IPC: G01R31/08 ; G06F11/00 ; H04J3/06 ; G06F15/173

Abstract:
There is disclosed a fault tolerant duplex computer system capable of increasing accuracy of processing to be continued by collecting trouble information without stopping duplex running. CPU's (112, 122), memories (113, 123), and IO processors (114, 124) of systems (110, 120) announce a reparable trouble to fault diagnosis processors (116, 126) when the generated trouble can be repaired, and an irreparable trouble when the generated trouble cannot be repaired. When an out-of-sync situation is confirmed, the out-of-sync situation is announced. A fault monitoring section (130) updates reparable trouble information (131) of a relevant system when the reparable trouble is received, and irreparable trouble information (132) of a relevant system when the irreparable trouble is received. Upon reception of the out-of-sync situation, a synchronous processing instruction is made by setting the system of a smaller amount of trouble information as an active system and the system of a larger number of trouble information as a standby system.
Public/Granted literature
- US20060133410A1 Fault tolerant duplex computer system and its control method Public/Granted day:2006-06-22
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