Invention Grant
US07751517B2 Multi-lane elastic buffer cluster for clock tolerance compensation and de-skew among multiple receiving lanes
有权
多通道弹性缓冲区,用于多个接收通道之间的时钟容差补偿和去偏移
- Patent Title: Multi-lane elastic buffer cluster for clock tolerance compensation and de-skew among multiple receiving lanes
- Patent Title (中): 多通道弹性缓冲区,用于多个接收通道之间的时钟容差补偿和去偏移
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Application No.: US11611412Application Date: 2006-12-15
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Publication No.: US07751517B2Publication Date: 2010-07-06
- Inventor: Henry Shi Li , Xinpeng Feng
- Applicant: Henry Shi Li , Xinpeng Feng
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Townsend and Townsend and Crew LLP
- Priority: CN200610119027 20061130
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
System and method for data transfer with buffer control. According to an embodiment, the present invention provides a system for synchronized data communication. The system includes a first communication interface for receiving data and a first clock signal. For example, the first clock signal is associated with a transmitting source. The system also includes a second communication interface for transmitting data. The system further includes a processing component for separating a single data stream into multiple data streams. The system additionally includes a clock that is configured to provide a second clock signal. Also, the system includes a plurality of buffer components for providing temporary storage for data streams. For example, each of the buffer components can be characterized by a predetermined buffer size. The plurality of buffering component includes a first buffer component and a second buffer component.
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