A timing generator and methods thereof are provided. In a first example method, a timing control signal may be produced by generating a base clock signal and a higher delay resolution clock signal, a clock cycle of the higher delay resolution signal being less than a clock cycle of the base clock signal. A first control word output signal may be generated by synchronizing a control word with the base clock signal. A second control word output signal may be generated by synchronizing the first control word output signal with the higher delay resolution clock signal and generating at least one additional control word output signal based on the second control word output signal and the higher delay resolution clock signal, the first, second and at least one additional control word output signal each having different delay resolutions. In a second example method, a timing control signal may be produced by generating a plurality of control word output signals, each of the plurality of control word output signals having a different delay resolution and selecting one of the plurality of control word output signals based on a delay resolution of the selected control word output signal, the delay resolution of the selected control word output signal better suited for interaction with an external device than delay resolutions of other of the plurality of control word output signals. A timing generator may be configured to perform either of the above-described first and second example methods.