Invention Grant
US07752377B2 Structure compatible with I2C bus and system management bus and timing buffering apparatus thereof
失效
与I2C总线和系统管理总线及其定时缓冲装置兼容的结构
- Patent Title: Structure compatible with I2C bus and system management bus and timing buffering apparatus thereof
- Patent Title (中): 与I2C总线和系统管理总线及其定时缓冲装置兼容的结构
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Application No.: US12015378Application Date: 2008-01-16
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Publication No.: US07752377B2Publication Date: 2010-07-06
- Inventor: Xiao-bing Zou , Shih-Hao Liu
- Applicant: Xiao-bing Zou , Shih-Hao Liu
- Applicant Address: TW Taipei
- Assignee: Inventec Corporation
- Current Assignee: Inventec Corporation
- Current Assignee Address: TW Taipei
- Agency: J.C. Patents
- Priority: TW96141576A 20071102
- Main IPC: G06F13/36
- IPC: G06F13/36
Abstract:
A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time.
Public/Granted literature
- US20090119439A1 STRUCTURE COMPATIBLE WITH I2C BUS AND SYSTEM MANAGEMENT BUS AND TIMING BUFFERING APPARATUS THEREOF Public/Granted day:2009-05-07
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