Invention Grant
- Patent Title: L1 cache flush when processor is entering low power mode
- Patent Title (中): 当处理器进入低功耗模式时，L1缓存刷新
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Application No.: US11525584Application Date: 2006-09-22
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Publication No.: US07752474B2Publication Date: 2010-07-06
- Inventor: James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
- Applicant: James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Lawrence J. Merkel
- Main IPC: G06F1/32
- IPC: G06F1/32
Abstract:
In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
Public/Granted literature
- US20080077813A1 Fast L1 flush mechanism Public/Granted day:2008-03-27
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