Invention Grant
- Patent Title: FIFO memory error circuit and method
- Patent Title (中): FIFO存储器错误电路和方法
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Application No.: US10891339Application Date: 2004-07-14
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Publication No.: US07752506B1Publication Date: 2010-07-06
- Inventor: Rishi Yadav
- Applicant: Rishi Yadav
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A FIFO memory error circuit has a read pointer coupled to a FIFO memory. The read pointer has a logic high output once every FIFO memory cycle. A write pointer is coupled to the FIFO memory and has a logic high output once every FIFO memory cycle. An error detector has a first input coupled to the read pointer and a second input coupled to the write pointer.
Information query
