Invention Grant
US07752515B2 Accelerated scan circuitry and method for reducing scan test data volume and execution time
有权
加速扫描电路和减少扫描测试数据量和执行时间的方法
- Patent Title: Accelerated scan circuitry and method for reducing scan test data volume and execution time
- Patent Title (中): 加速扫描电路和减少扫描测试数据量和执行时间的方法
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Application No.: US11680684Application Date: 2007-03-01
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Publication No.: US07752515B2Publication Date: 2010-07-06
- Inventor: Bulent I. Dervisoglu , Laurence H. Cooke
- Applicant: Bulent I. Dervisoglu , Laurence H. Cooke
- Agency: Connolly Bove Lodge & Hutz LLP
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
Public/Granted literature
- US20070162803A1 Accelerated Scan Circuitry and Method for Reducing Scan Test Data Volume and Execution Time Public/Granted day:2007-07-12
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