Invention Grant
- Patent Title: System and method for increasing the extent of built-in self-testing of memory and circuitry
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Application No.: US12030365Application Date: 2008-02-13
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Publication No.: US07752518B2Publication Date: 2010-07-06
- Inventor: Cloves R. Cleavelin , Andrew Marshall , Stephanie W. Butler , Howard L. Tigelaar
- Applicant: Cloves R. Cleavelin , Andrew Marshall , Stephanie W. Butler , Howard L. Tigelaar
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G01R31/28

Abstract:
An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.
Public/Granted literature
- US20090204861A1 System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry Public/Granted day:2009-08-13
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