Invention Grant
US07752520B2 Apparatus and method capable of a unified quasi-cyclic low-density parity-check structure for variable code rates and sizes
有权
能够实现统一的准循环低密度奇偶校验结构的装置和方法，用于可变码率和大小
- Patent Title: Apparatus and method capable of a unified quasi-cyclic low-density parity-check structure for variable code rates and sizes
- Patent Title (中): 能够实现统一的准循环低密度奇偶校验结构的装置和方法，用于可变码率和大小
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Application No.: US10997581Application Date: 2004-11-24
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Publication No.: US07752520B2Publication Date: 2010-07-06
- Inventor: Bo Xia
- Applicant: Bo Xia
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
An embodiment of the present invention provides an apparatus, comprising a transceiver capable of a unified quasi-cyclic low-density parity-check structure for variable code rates and sizes using a unified base matrix definition. This base matrix definition may be a concatenation of multiple square matrices Sm×Rm=(Sm×mR|Sm×mR−1| . . . |Sm×m3|Sm×m2|Sm×m1) and the base matrix for rate (r−1)/r may be Sm×rm=(Sm×mr|Sm×mr−1| . . . |Sm×m3|Sm×m2|Sm×m1) for r=2, 3, . . . , R.
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