Invention Grant
US07754551B2 Method for making very low Vt metal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions
有权
制造非常低的Vt金属栅极/高压晶体管的方法 CMOSFET采用自对准低温浅结
- Patent Title: Method for making very low Vt metal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions
- Patent Title (中): 制造非常低的Vt金属栅极/高压晶体管的方法 CMOSFET采用自对准低温浅结
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Application No.: US12216561Application Date: 2008-07-08
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Publication No.: US07754551B2Publication Date: 2010-07-13
- Inventor: Albert Chin
- Applicant: Albert Chin
- Applicant Address: TW Hsinchu
- Assignee: National Chiao Tung University
- Current Assignee: National Chiao Tung University
- Current Assignee Address: TW Hsinchu
- Agency: Bacon & Thomas, PLLC
- Priority: TW97116760A 20080507
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/84 ; H01L21/338 ; H01L21/22 ; H01L21/38
Abstract:
This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability
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