Invention Grant
- Patent Title: Methods for fabricating low contact resistance CMOS circuits
- Patent Title (中): 制造低接触电阻CMOS电路的方法
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Application No.: US11669401Application Date: 2007-01-31
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Publication No.: US07754554B2Publication Date: 2010-07-13
- Inventor: Igor Peidous , Patrick Press , Paul R. Besser
- Applicant: Igor Peidous , Patrick Press , Paul R. Besser
- Applicant Address: KY Grand Cayman
- Assignee: GlobalFoundries Inc.
- Current Assignee: GlobalFoundries Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
Methods for fabricating low contact resistance CMOS integrated circuits are provided. In accordance with an embodiment, a method for fabricating a CMOS integrated circuit including an NMOS transistor and a PMOS transistor disposed in and on a silicon-comprising substrate includes depositing a first silicide-forming metal on the NMOS and PMOS transistors. The first silicide-forming metal forms a silicide at a first temperature. At least a portion of the first silicide-forming metal is removed from the NMOS or PMOS transistor and a second silicide-forming metal is deposited. The second silicide-forming metal forms a silicide at a second temperature that is different from the first temperature. The first silicide-forming metal and the second silicide-forming metal are heated at a temperature that is no less than the higher of the first temperature and the second temperature.
Public/Granted literature
- US20080182370A1 METHODS FOR FABRICATING LOW CONTACT RESISTANCE CMOS CIRCUITS Public/Granted day:2008-07-31
Information query
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