A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.