Invention Grant
- Patent Title: Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process
- Patent Title (中): 集成在半导体衬底上的多漏极型功率电子器件及相关制造工艺
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Application No.: US12350763Application Date: 2009-01-08
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Publication No.: US07754566B2Publication Date: 2010-07-13
- Inventor: Mario Guiseppe Saggio , Ferruccio Frisina
- Applicant: Mario Guiseppe Saggio , Ferruccio Frisina
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Gardere Wynne Sewell LLP
- Priority: EP05425102 20050225
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.
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