Invention Grant
- Patent Title: Method for examining bonding resistance
- Patent Title (中): 检查接合电阻的方法
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Application No.: US11985087Application Date: 2007-11-13
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Publication No.: US07755370B2Publication Date: 2010-07-13
- Inventor: De-Ching Shie
- Applicant: De-Ching Shie
- Applicant Address: TW Miao-Li County
- Assignee: Innolux Display Corp.
- Current Assignee: Innolux Display Corp.
- Current Assignee Address: TW Miao-Li County
- Agent Wei Te Chung
- Priority: TW95141776A 20061110
- Main IPC: G01R27/08
- IPC: G01R27/08 ; G01R31/00

Abstract:
An exemplary method for examining bonding resistance includes providing a first electronic component having a first and second reference pins. A second electronic component having a third and fourth reference pins is also provided. A first input voltage is applied to the first reference pin. A bias resistor connected between the third reference pin and ground is provided, with the third reference pin serving as an output for providing a first reference voltage. The first reference voltage is measured. Bonding resistance between the first reference pin and the third reference pin is evaluated according to the measured first reference voltage.
Public/Granted literature
- US20080111564A1 Method for examining bonding resistance Public/Granted day:2008-05-15
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