Invention Grant
- Patent Title: Three-valued logic function circuit
- Patent Title (中): 三值逻辑函数电路
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Application No.: US12162760Application Date: 2007-01-31
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Publication No.: US07755391B2Publication Date: 2010-07-13
- Inventor: Yasushi Hibino , Masaaki Shirase
- Applicant: Yasushi Hibino , Masaaki Shirase
- Applicant Address: JP Ishikawa
- Assignee: Japan Advanced Institute of Science and Technology
- Current Assignee: Japan Advanced Institute of Science and Technology
- Current Assignee Address: JP Ishikawa
- Agency: Foley & Lardner LLP
- Priority: JP2006-023474 20060131
- International Application: PCT/JP2007/051620 WO 20070131
- International Announcement: WO2007/088901 WO 20070809
- Main IPC: H03K19/00
- IPC: H03K19/00 ; H03K19/02

Abstract:
There is provided a three-valued logic function circuit capable of remarkably reducing the kinds of basic circuits necessary for realizing all 33^2=19683 kinds of two-variable three-valued logic function circuits, remarkably reducing asymmetry of the switching time, and improving an operation speed and symmetry of waveform of the logic function circuit. In a three-valued logic function circuit, three transfer gates T1, T2, and T3 are turned on or off by one-variable three-valued logic function circuits C1, D1, C3 and D3, according to three logic values −1, 0, and 1 constituting a first input a, to select outputs of three one-variable three-valued logic function circuits B1, B2, and B3 connected to a second input b. The transfer gate T2 is configured by parallel connection of a switch pair of serial connection of two n-type MOS transistors and a switch pair of serial connection of two p-type MOS transistors.
Public/Granted literature
- US20090295428A1 THREE-VALUED LOGIC FUNCTION CIRCUIT Public/Granted day:2009-12-03
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