Invention Grant
- Patent Title: High speed comparator circuit with offset cancellation
- Patent Title (中): 具有偏移消除的高速比较器电路
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Application No.: US11960284Application Date: 2007-12-19
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Publication No.: US07755399B2Publication Date: 2010-07-13
- Inventor: Toshiyuki Uchida
- Applicant: Toshiyuki Uchida
- Applicant Address: JP Chiba
- Assignee: Seiko Instruments Inc.
- Current Assignee: Seiko Instruments Inc.
- Current Assignee Address: JP Chiba
- Agency: Brinks Hofer Gilson & Lione
- Priority: JP2006-344413 20061221; JP2007-291686 20071109
- Main IPC: G11C27/02
- IPC: G11C27/02

Abstract:
Provided is a comparator circuit that is capable of operating at high speed and canceling an offset voltage with high precision. The comparator circuit includes a second amplifier circuit for amplifying an output of an amplifier circuit and feeding back the amplified output to an input of the amplifier circuit. When the comparator circuit samples the input voltage, the second amplifier circuit conducts feedback and increases a gain to cancel the offset. Also, when the gain of the amplifier circuit is made lower than the gain of the second amplifier circuit, and the comparator circuit compares the input voltage, the comparing operation can be conducted at high speed by separating the amplifier circuit from the feedback of the second amplifier circuit.
Public/Granted literature
- US20080197887A1 Comparator Circuit Public/Granted day:2008-08-21
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