Invention Grant
US07755448B2 Differential impedance matching circuit and method with harmonic suppression 有权
差分阻抗匹配电路及谐波抑制方法

Differential impedance matching circuit and method with harmonic suppression
Abstract:
Matching network circuits and a method are shown for suppressing a harmonic frequency in a matching network. The circuits and method involve impedance matching first and second differential input nodes to a single ended output node using a first reactive impedance selected to pass a resonant frequency. They also involve suppressing a harmonic frequency of a common mode signal presented at the first and second differential input nodes by providing a series resonance from the first and second differential input nodes to a radio frequency ground potential, where the series resonance is selected to pass the harmonic frequency to the radio frequency ground potential.
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