Invention Grant
- Patent Title: Differential impedance matching circuit and method with harmonic suppression
- Patent Title (中): 差分阻抗匹配电路及谐波抑制方法
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Application No.: US11970237Application Date: 2008-01-07
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Publication No.: US07755448B2Publication Date: 2010-07-13
- Inventor: Attila Zolomy , Peter Onody , Tibor Toro
- Applicant: Attila Zolomy , Peter Onody , Tibor Toro
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: O'Keefe, Egan, Peterman & Enders LLP
- Main IPC: H03H7/38
- IPC: H03H7/38

Abstract:
Matching network circuits and a method are shown for suppressing a harmonic frequency in a matching network. The circuits and method involve impedance matching first and second differential input nodes to a single ended output node using a first reactive impedance selected to pass a resonant frequency. They also involve suppressing a harmonic frequency of a common mode signal presented at the first and second differential input nodes by providing a series resonance from the first and second differential input nodes to a radio frequency ground potential, where the series resonance is selected to pass the harmonic frequency to the radio frequency ground potential.
Public/Granted literature
- US20080174383A1 DIFFERENTIAL IMPEDANCE MATCHING CIRCUIT AND METHOD WITH HARMONIC SUPPRESSION Public/Granted day:2008-07-24
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