A memory cell array includes a plurality of memory cells disposed in matrix. A plurality of word lines extend in the row direction, and the gates in the memory cells disposed in each row are commonly connected to one of the word lines. A plurality of sub bit lines extend in the column direction, and the sources in the memory cells disposed in a first column and the drains in the memory cells disposed in a second column, which is adjacent to the first column, are commonly connected to one of the sub bit lines. A plurality of pairs of transistors are provided, each having a source selector and a drain selector. Each transistor pair is disposed at one of the locations at both ends of the sub bit lines, which are adjacent to each other, in a manner such that the transistor pairs sandwich the word lines from alternating sub bit ends.