Invention Grant
US07757046B2 Method and apparatus for optimizing line writes in cache coherent systems
失效
用于优化高速缓存一致系统中线路写入的方法和装置
- Patent Title: Method and apparatus for optimizing line writes in cache coherent systems
- Patent Title (中): 用于优化高速缓存一致系统中线路写入的方法和装置
-
Application No.: US10262363Application Date: 2002-09-30
-
Publication No.: US07757046B2Publication Date: 2010-07-13
- Inventor: Sujat Jamil , Hang T. Nguyen , Samantha J. Edirisooriya , David E. Miner , R. Frank O'Bleness , Steven J. Tu
- Applicant: Sujat Jamil , Hang T. Nguyen , Samantha J. Edirisooriya , David E. Miner , R. Frank O'Bleness , Steven J. Tu
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F12/12
- IPC: G06F12/12

Abstract:
A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.
Public/Granted literature
- US20040064643A1 Method and apparatus for optimizing line writes in cache coherent systems Public/Granted day:2004-04-01
Information query