An integrated circuit (IC) having a memory built-in self-test (MBIST) controller. The IC includes an MBIST controller and a plurality of memory arrays. One or more the memory arrays has a different physical organization with respect to other ones of the memory arrays. The MBIST controller is configured to generate a logical address of a memory under test. The MBIST controller is further configured to permute the bits to produce a physical address. The user programmed permutation enables a simple address incrementer to create an address sequence that traverses the physical organization of the memory in accordance with the type of desired test.