Invention Grant
- Patent Title: Semiconductor device having reduced single bit fails and a method of manufacture thereof
- Patent Title (中): 具有减少的单位故障的半导体器件及其制造方法
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Application No.: US11845834Application Date: 2007-08-28
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Publication No.: US07772014B2Publication Date: 2010-08-10
- Inventor: Kezhakkedath R. Udayakumar , Ted S. Moise , Qi-Du Jiang
- Applicant: Kezhakkedath R. Udayakumar , Ted S. Moise , Qi-Du Jiang
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H01L29/92
- IPC: H01L29/92

Abstract:
One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.
Public/Granted literature
- US20090057736A1 Semiconductor Device Having Reduced Single Bit Fails and a Method of Manufacture Thereof Public/Granted day:2009-03-05
Information query
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