Invention Grant
- Patent Title: Semiconductor device containing a buried threshold voltage adjustment layer and method of forming
- Patent Title (中): 包含掩埋阈值电压调节层的半导体器件及其形成方法
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Application No.: US11864514Application Date: 2007-09-28
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Publication No.: US07772073B2Publication Date: 2010-08-10
- Inventor: Robert D. Clark , Gerrit J. Leusink
- Applicant: Robert D. Clark , Gerrit J. Leusink
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.
Public/Granted literature
- US20090085175A1 SEMICONDUCTOR DEVICE CONTAINING A BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYER AND METHOD OF FORMING Public/Granted day:2009-04-02
Information query
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