Invention Grant
- Patent Title: Semiconductor device with large blocking voltage and method of manufacturing the same
- Patent Title (中): 具有大阻断电压的半导体器件及其制造方法
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Application No.: US12533740Application Date: 2009-07-31
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Publication No.: US07772613B2Publication Date: 2010-08-10
- Inventor: Haruka Shimizu , Natsuki Yokoyama
- Applicant: Haruka Shimizu , Natsuki Yokoyama
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, P.C.
- Priority: JP2008-200397 20080804
- Main IPC: H01L29/80
- IPC: H01L29/80

Abstract:
A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.
Public/Granted literature
- US20100025739A1 SEMICONDUCTOR DEVICE WITH LARGE BLOCKING VOLTAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2010-02-04
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