Invention Grant
- Patent Title: DRAM cells with vertical transistors
- Patent Title (中): 具有垂直晶体管的DRAM单元
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Application No.: US12339610Application Date: 2008-12-19
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Publication No.: US07772633B2Publication Date: 2010-08-10
- Inventor: Werner Juengling
- Applicant: Werner Juengling
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/94

Abstract:
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.
Public/Granted literature
- US20090096000A1 DRAM CELLS WITH VERTICAL TRANSISTORS Public/Granted day:2009-04-16
Information query
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