Invention Grant
US07772647B2 Structure and design structure having isolated back gates for fully depleted SOI devices
失效
具有完全耗尽的SOI器件的隔离背栅的结构和设计结构
- Patent Title: Structure and design structure having isolated back gates for fully depleted SOI devices
- Patent Title (中): 具有完全耗尽的SOI器件的隔离背栅的结构和设计结构
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Application No.: US12136213Application Date: 2008-06-10
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Publication No.: US07772647B2Publication Date: 2010-08-10
- Inventor: Brent A. Anderson , Edward J. Nowak
- Applicant: Brent A. Anderson , Edward J. Nowak
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Anthony Canale
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well therein of opposite polarity than the first polarity; forming a trench structure in the FDSOI substrate; forming an active region to each side of the trench structure in the SOI layer; and forming a PFET on the active region on one side of the trench structure and an NFET on the active region on the other side of the trench structure.
Public/Granted literature
- US20090302366A1 STRUCTURE AND DESIGN STRUCTURE HAVING ISOLATED BACK GATES FOR FULLY DEPLETED SOI DEVICES Public/Granted day:2009-12-10
Information query
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