Invention Grant
US07772647B2 Structure and design structure having isolated back gates for fully depleted SOI devices 失效
具有完全耗尽的SOI器件的隔离背栅的结构和设计结构

Structure and design structure having isolated back gates for fully depleted SOI devices
Abstract:
Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well therein of opposite polarity than the first polarity; forming a trench structure in the FDSOI substrate; forming an active region to each side of the trench structure in the SOI layer; and forming a PFET on the active region on one side of the trench structure and an NFET on the active region on the other side of the trench structure.
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