Invention Grant
- Patent Title: Semiconductor constructions
- Patent Title (中): 半导体结构
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Application No.: US11218231Application Date: 2005-09-01
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Publication No.: US07772672B2Publication Date: 2010-08-10
- Inventor: Zailong Bian , Janos Fucsko
- Applicant: Zailong Bian , Janos Fucsko
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/00
- IPC: H01L29/00

Abstract:
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
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