Invention Grant
- Patent Title: Systems and methods for testing packaged dies
- Patent Title (中): 包装模具的测试系统和方法
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Application No.: US11436452Application Date: 2006-05-18
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Publication No.: US07772831B2Publication Date: 2010-08-10
- Inventor: Tauseef Kazi , Jeff Gemar , Vaishnav Srinivas , Vivek Mohan
- Applicant: Tauseef Kazi , Jeff Gemar , Vaishnav Srinivas , Vivek Mohan
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter M. Kamarchik; Nicholas J. Pauley; Sam Talpalatsky
- Main IPC: H01L23/02
- IPC: H01L23/02 ; G01R31/26

Abstract:
A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.
Public/Granted literature
- US20060214276A1 Systems and methods for testing packaged dies Public/Granted day:2006-09-28
Information query
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