Invention Grant
- Patent Title: Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection
- Patent Title (中): 集成电路检测信号强度与表面电压映射的结构和方法
-
Application No.: US11683058Application Date: 2007-03-07
-
Publication No.: US07772866B2Publication Date: 2010-08-10
- Inventor: Oliver D. Patterson , Horatio Seymour Wildman , Min-Chul Sun
- Applicant: Oliver D. Patterson , Horatio Seymour Wildman , Min-Chul Sun
- Applicant Address: US NY Armonk KR Gyeonggi-Do
- Assignee: International Business Machines Corporation,Samsung Electronics Co., Ltd.
- Current Assignee: International Business Machines Corporation,Samsung Electronics Co., Ltd.
- Current Assignee Address: US NY Armonk KR Gyeonggi-Do
- Agent Yuanmin Cai
- Main IPC: G01R31/02
- IPC: G01R31/02

Abstract:
Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.
Public/Granted literature
- US20080217612A1 STRUCTURE AND METHOD OF MAPPING SIGNAL INTENSITY TO SURFACE VOLTAGE FOR INTEGRATED CIRCUIT INSPECTION Public/Granted day:2008-09-11
Information query