Invention Grant
US07772866B2 Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection 失效
集成电路检测信号强度与表面电压映射的结构和方法

Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection
Abstract:
Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.
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