Invention Grant
- Patent Title: Input/output circuit for evaluating delay
- Patent Title (中): 用于评估延迟的输入/输出电路
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Application No.: US12158121Application Date: 2006-12-18
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Publication No.: US07772875B2Publication Date: 2010-08-10
- Inventor: Mukesh Nair
- Applicant: Mukesh Nair
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP05112655 20051221
- International Application: PCT/IB2006/054919 WO 20061218
- International Announcement: WO2007/072398 WO 20070628
- Main IPC: H03K19/003
- IPC: H03K19/003

Abstract:
An electronic device comprising at least one input/output circuit (10) in a first supply voltage domain (VDD, GND) is provided. The electronic device furthermore comprises a buffer (INV) which is coupled to the input/output circuit for driving an input of the input/output circuit (10). The buffer comprises a first and second switch (T1, T2; T4, T5). The buffer is arranged in a second supply voltage domain (VDD1, GND1). Furthermore, a control circuit is coupled to the buffer for controlling the first and second switch (T1, T2; T4, T5) such that during a transition of an input signal of the input/output circuit (10) both switches (T1, T2; T4, T5) are temporarily kept in a conducting state and a crowbar current flows through the buffer (INV).
Public/Granted literature
- US20080272799A1 Electronic Device Public/Granted day:2008-11-06
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