Invention Grant
US07772877B2 Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method
有权
输出缓冲电路,差分输出缓冲电路,具有调节电路和调节功能的输出缓冲电路及传输方式
- Patent Title: Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method
- Patent Title (中): 输出缓冲电路,差分输出缓冲电路,具有调节电路和调节功能的输出缓冲电路及传输方式
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Application No.: US12343521Application Date: 2008-12-24
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Publication No.: US07772877B2Publication Date: 2010-08-10
- Inventor: Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
- Applicant: Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2007-339602 20071228
- Main IPC: H03K19/003
- IPC: H03K19/003

Abstract:
An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
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