Provided is a level shift circuit. The level shift circuit includes an inverter including a first transistor having a first polarity to which an input signal from an input port is applied through a gate and a second transistor having a second polarity which is an opposite polarity to the first polarity, the second transistor being connected in series to the first transistor between a positive source voltage and a negative source voltage and a connection node between the first and second transistors being an output port, a capacitor connected between a gate of the first transistor and a gate of the second transistor, and a voltage adjusting means for accurately adjusting a voltage applied to the gate of the second transistor according to an exact switching operation time of the second transistor, using a clock signal and an output port signal of the inverter. A stable and high-speed operation can be performed with a comparatively small size and low power consumption can be achieved.