A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit.