Invention Grant
- Patent Title: Image forming processing circuit and image forming apparatus
- Patent Title (中): 图像形成处理电路和图像形成装置
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Application No.: US11421735Application Date: 2006-06-01
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Publication No.: US07773236B2Publication Date: 2010-08-10
- Inventor: Junji Yamada
- Applicant: Junji Yamada
- Applicant Address: JP Tokyo JP Tokyo
- Assignee: Toshiba Tec Kabushiki Kaisha,Kabushiki Kaisha Toshiba
- Current Assignee: Toshiba Tec Kabushiki Kaisha,Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Main IPC: G06F3/12
- IPC: G06F3/12 ; G06K15/00

Abstract:
An image forming processing circuit and an image forming apparatus having a clock stop function of the invention perform, in an image forming processing process, supply of a clock for processing only in a period in which the clock is required and stop the supply of the clock for processing in a period in which the clock for processing is not required. An ASIC itself realizes a low power consumption function (a clock stop function) without requiring control from a CPU or the like as in the conventional sleep function. Thus, it is possible to effectively reduce power consumption of the ASIC compared with that in the past.
Public/Granted literature
- US20070280512A1 Image Forming Processing Circuit and Image Forming Apparatus Public/Granted day:2007-12-06
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