Invention Grant
US07773447B2 Memory circuit, semiconductor device and read control method of memory circuit
有权
存储电路,半导体器件和存储电路的读取控制方法
- Patent Title: Memory circuit, semiconductor device and read control method of memory circuit
- Patent Title (中): 存储电路,半导体器件和存储电路的读取控制方法
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Application No.: US11976853Application Date: 2007-10-29
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Publication No.: US07773447B2Publication Date: 2010-08-10
- Inventor: Kazuhiko Kajigaya
- Applicant: Kazuhiko Kajigaya
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2006-294996 20061030
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
A memory circuit of the invention comprises N look-up tables for implementing a desired logic function of L inputs/M outputs by partitioning a memory cell array including a plurality of memory cells into portions each corresponding to at least a predetermined number of input/output paths; a decode circuit for selecting one of the N look-up tables by decoding a look-up table select signal and for selecting M memory cells to be accessed included in the selected look-up table by decoding an L-bit logic input signal of the logic function; and a select connect circuit for selectively connecting the input/output paths of the M memory cells to be accessed with an input/output bus for transmitting an M-bit logic output signal of the logic function in response to a decoded result of the decode circuit.
Public/Granted literature
- US20080100337A1 Memory circuit, semiconductor device and read control method of memory circuit Public/Granted day:2008-05-01
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