Invention Grant
- Patent Title: Clock switching circuit
- Patent Title (中): 时钟切换电路
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Application No.: US11822328Application Date: 2007-07-05
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Publication No.: US07773712B2Publication Date: 2010-08-10
- Inventor: Akimitsu Ikeda
- Applicant: Akimitsu Ikeda
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2006-186619 20060706
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A clock switching circuit in which one clock signal is selected from 2N-phase input clock signals with the same frequency but with each shifted in phase (where N is an integer equal to or greater than 3), based on N-bit selection signals, and is output as an output clock signal, comprises a selector group having 2N−1 selectors each of which select and output one clock signal from two input clock signals, and an operation control circuit which generates 2N−1 operation control signals to execute control to set the 2N−1 selectors into an active state or into a sleep state. The selectors select the clock signals based on the selection signals. The operation control circuit executes control to set a portion of the selectors among the 2N−1 selectors to the active state and to set the remaining selectors to the sleep state, based on the selection signals.
Public/Granted literature
- US20080008282A1 Clock switching circuit Public/Granted day:2008-01-10
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