Invention Grant
- Patent Title: Apparatus and method for validating a computer model
- Patent Title (中): 用于验证计算机模型的装置和方法
-
Application No.: US12208141Application Date: 2008-09-10
-
Publication No.: US07774182B2Publication Date: 2010-08-10
- Inventor: Thomas Paterson
- Applicant: Thomas Paterson
- Applicant Address: US CA Foster City
- Assignee: Entelos, Inc.
- Current Assignee: Entelos, Inc.
- Current Assignee Address: US CA Foster City
- Agent Karen E. Flick
- Main IPC: G06F17/10
- IPC: G06F17/10

Abstract:
An apparatus and method for validating a computer model is described. In one embodiment, a computer-readable medium comprises instructions to associate a set of configurations of a computer model with a stimulus-response test, each configuration of the set of configurations representing a different model scenario, the stimulus-response test defining a modification to each configuration of the set of configurations. The computer-readable medium also comprises instructions to apply the stimulus-response test to the set of configurations to produce a simulated response for each configuration of the set of configurations and instructions to compare the simulated responses for the set of configurations with an expected response to the stimulus-response test.
Public/Granted literature
- US20090132219A1 Apparatus and Method for Validating a Computer Model Public/Granted day:2009-05-21
Information query