A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.