Invention Grant
- Patent Title: Memory system and memory device
- Patent Title (中): 内存系统和内存设备
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Application No.: US12428370Application Date: 2009-04-22
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Publication No.: US07774535B2Publication Date: 2010-08-10
- Inventor: Nobutaka Nakamura
- Applicant: Nobutaka Nakamura
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2008-160692 20080619
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
According to one embodiment, a first memory device is configured to receive write data from a controller and transmit read data to the controller via a first data pin included in the first memory device. The second memory device is configured to receive write data from the controller and transmit read data to the controller via a second data pin included in the second memory device. A redelivery module within the first memory device is configured to receive an address and a command output from the controller via a predetermined signal line, and output the address and the command to the second memory device via remaining first data pin.
Public/Granted literature
- US20090319748A1 MEMORY SYSTEM AND MEMORY DEVICE Public/Granted day:2009-12-24
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