Invention Grant
- Patent Title: Lithography method for forming a circuit pattern
- Patent Title (中): 用于形成电路图案的平版印刷方法
-
Application No.: US11897600Application Date: 2007-08-31
-
Publication No.: US07774738B2Publication Date: 2010-08-10
- Inventor: Jae In Moon
- Applicant: Jae In Moon
- Applicant Address: KR Icheon-si
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-si
- Agency: Marshall, Gerstein & Borun LLP
- Priority: KR10-2007-0028623 20070323
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A lithography method for suppressing resist scum includes the steps of designing an original layout with line patterns and pad patterns, extracting a pad pattern layout from the original, layout, obtaining a first reduction layout which is reduced by a first reduction width relative to the pad pattern layout, obtaining a second reduction layout which is reduced by a second reduction width larger than the first reduction width relative to the pad pattern layout, obtaining an assist pattern layout which is self-aligned to the pad pattern layout by deducting the second reduction layout from the first reduction layout, generating assist patterns in the original layout by deducting the assist pattern layout from the original layout, and projecting the layout including the assist patterns on a semiconductor substrate by an exposure process.
Public/Granted literature
- US20080235652A1 Lithography method for forming a circuit pattern Public/Granted day:2008-09-25
Information query