Invention Grant
US07781235B2 Chip-probing and bumping solutions for stacked dies having through-silicon vias
有权
具有通硅通孔的堆叠管芯的芯片探测和碰撞解决方案
- Patent Title: Chip-probing and bumping solutions for stacked dies having through-silicon vias
- Patent Title (中): 具有通硅通孔的堆叠管芯的芯片探测和碰撞解决方案
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Application No.: US11644397Application Date: 2006-12-21
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Publication No.: US07781235B2Publication Date: 2010-08-24
- Inventor: Wen-Liang Luo , Yung-Liang Kuo , Hsu Ming Cheng
- Applicant: Wen-Liang Luo , Yung-Liang Kuo , Hsu Ming Cheng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/66
- IPC: H01L21/66

Abstract:
A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs) connected to the plurality of through-silicon vias, wherein the UBMs are on the first side of the stack structure. The method further includes attaching a handling wafer on the second side of the stack structure; performing a chip probing process; and removing the handling wafer from the stack structure.
Public/Granted literature
- US20080153187A1 Chip-probing and bumping solutions for stacked dies having through-silicon vias Public/Granted day:2008-06-26
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