Invention Grant
- Patent Title: DFN semiconductor package having reduced electrical resistance
- Patent Title (中): DFN半导体封装具有降低的电阻
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Application No.: US12384100Application Date: 2009-03-30
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Publication No.: US07781265B2Publication Date: 2010-08-24
- Inventor: Xiaotian Zhang , Kai Liu , Ming Sun
- Applicant: Xiaotian Zhang , Kai Liu , Ming Sun
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agency: Schein & Cai LLP
- Agent Jingming Cai
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50
Abstract:
A dual flat non-leaded semiconductor package is disclosed. A method of making a dual flat non-leaded semiconductor package includes forming a leadframe having a die bonding area with an integral drain lead, a gate lead bonding area and a source lead bonding area, the gate lead bonding area and a source lead bonding area being of increased area; bonding a die to the die bonding area; coupling a die source bonding area to the source lead bonding area; coupling a die gate bonding area to the gate lead bonding area; and partially encapsulating the die, the drain lead, the gate lead and the source lead to form the dual flat non-leaded semiconductor package.
Public/Granted literature
- US20090258458A1 DFN semiconductor package having reduced electrical resistance Public/Granted day:2009-10-15
Information query
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