Invention Grant
US07781280B2 Semiconductor device with capacitor and fuse and its manufacture method
有权
具有电容器和保险丝的半导体器件及其制造方法
- Patent Title: Semiconductor device with capacitor and fuse and its manufacture method
- Patent Title (中): 具有电容器和保险丝的半导体器件及其制造方法
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Application No.: US11797483Application Date: 2007-05-03
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Publication No.: US07781280B2Publication Date: 2010-08-24
- Inventor: Masayoshi Omura
- Applicant: Masayoshi Omura
- Applicant Address: JP Shizuoka-ken
- Assignee: Yamaha Corporation
- Current Assignee: Yamaha Corporation
- Current Assignee Address: JP Shizuoka-ken
- Agency: Dickstein Shapiro LLP
- Priority: JP2003-364829 20031024; JP2004-298403 20041013
- Main IPC: H01L21/8249
- IPC: H01L21/8249

Abstract:
An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.
Public/Granted literature
- US20070207579A1 Semiconductor device with capacitor and fuse and its manufacture method Public/Granted day:2007-09-06
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