Invention Grant
US07781898B2 IC package reducing wiring layers on substrate and its chip carrier
有权
IC封装减少衬底及其芯片载体上的布线层
- Patent Title: IC package reducing wiring layers on substrate and its chip carrier
- Patent Title (中): IC封装减少衬底及其芯片载体上的布线层
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Application No.: US11806023Application Date: 2007-05-29
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Publication No.: US07781898B2Publication Date: 2010-08-24
- Inventor: Hung-Tsun Lin , Wu-Chang Tu , Cheng-Ting Wu
- Applicant: Hung-Tsun Lin , Wu-Chang Tu , Cheng-Ting Wu
- Applicant Address: TW Hsinchu
- Assignee: Chipmos Technologies Inc.
- Current Assignee: Chipmos Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C.
- Agent Anthony King
- Priority: TW96102754A 20070124
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.
Public/Granted literature
- US20080174031A1 Chip package reducing wiring layers on substrate and its carrier Public/Granted day:2008-07-24
Information query
IPC分类: