A timing controller including a memory and a memory controller is provided. The memory includes an odd-field block and an even-field block. The memory controller is coupled to the memory and controls the memory. When two of a first, a second and a third gate output enable signals output by the timing controller are active, the memory is controlled to output the data of the (I−1)th scan line stored in the odd-field block. When one of the first, the second and the third gate output enable signals output by the timing controller is active, and the other two signals are inactive, the memory is controlled to output the data of Jth scan line stored in the even-field block and write an odd-field field data of the (J+1)th scan line to the odd-field block and write an even-field field data of the (J+1)th scan line to the even-field block.